Scalable Parity Architecture With a Shuttling-Based Spin Qubit Processor

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The Parity Architecture is implemented on a two-dimensional square lattice of quantum dots. The authors construct sequences of spin shuttling and quantum gates that run the Parity Quantum Approximate Optimization Algorithm at constant circuit depth on a lattice built from identical unit cells, and model shuttling errors from the valley-splitting distribution. Compared with superconducting transmon qubits, spin qubits with high-fidelity shuttling perform competitively — near-term devices could reach error rates low enough to run short-depth Parity QAOA with a favourable success probability.

Constant-depth Parity QAOA on a lattice of identical unit cells