ArchitectureDraft
Why shuttling beats wiring
Dense spin-qubit arrays run out of room for their own control lines. Moving the electron instead of adding a wire is what turns a register into an architecture.
Research & insights
Every claim here has a paper behind it.
The architecture was developed in the open: at the JARA-Institute for Quantum Information, with Forschungszentrum Jülich and RWTH Aachen. Shuttling fidelity, valley-splitting maps, error-correction thresholds — the full record, with abstracts and reading view.
12
Publications in the library
4
Peer-reviewed journals
4
Founders, 20+ years in the field
Key recent papers
Jump to the full libraryConveyor-mode electron shuttling through a T-junction in Si/SiGe
Inter-lane charge transfer fidelity of 100.0000000 % (−9×10⁻⁷) at 270 mm s⁻¹
The SpinBus architecture for scaling spin qubits with electron shuttling
Operation fidelities exceeding 99.9 % in full device simulation
Spin-EPR-pair separation by conveyor-mode single electron shuttling in Si/SiGe
Shuttle velocity increased by a factor of 10 000 — entanglement still detectable after 3.36 µm
12 entries · 2017–2026
- 2026
Mapping g-factors and complex intervalley coupling in Si/SiGe by conveyor-mode shuttling
Mats Volmer, Tom Struck, Arnau Sala, Jhih-Sian Tu, Stefan Trellenkamp … +5 authors
g-factor variations resolved to better than 10⁻³ with nanometre resolution
Materials & valley physicsElectron shuttling - 2026
Conveyor-mode electron shuttling through a T-junction in Si/SiGe
Max Beer, Ran Xue, Lennart Deda, Stefan Trellenkamp, Jhih-Sian Tu … +4 authors
Inter-lane charge transfer fidelity of 100.0000000 % (−9×10⁻⁷) at 270 mm s⁻¹
Electron shuttlingArchitecture - 2025
Performance of the spin qubit shuttling architecture for a surface code implementation
Berat Yenilen, Arnau Sala, Hendrik Bluhm, Markus Müller, Manuel Rispler
Surface-code thresholds of several percent for dephasing-dominated shuttling errors
Quantum error correctionTheory & simulation - 2024
Long distance spin shuttling enabled by few-parameter velocity optimization
Alessandro David, Akshay Menon Pazhedath, Lars R. Schreiber, Tommaso Calarco, Hendrik Bluhm, Felix Motzoi
Below fault-tolerance thresholds with as few as four Fourier components
Electron shuttlingTheory & simulation - 2024
Scalable Parity Architecture With a Shuttling-Based Spin Qubit Processor
Florian Ginzel, Michael Fellner, Christian Ertler, Lars R. Schreiber, Hendrik Bluhm, Wolfgang Lechner
Constant-depth Parity QAOA on a lattice of identical unit cells
ArchitectureQuantum error correction - 2024
Mapping of valley-splitting by conveyor-mode spin-coherent electron shuttling
Mats Volmer, Tom Struck, Arnau Sala, Bingjie Chen, Max Oberländer … +8 authors
Sub-µeV energy accuracy with nanometre lateral resolution
Materials & valley physicsElectron shuttling - 2024
The SpinBus architecture for scaling spin qubits with electron shuttling
Matthias Künne, Alexander Willmes, Max Oberländer, Christian Gorjaew, Julian D. Teske … +8 authors
Operation fidelities exceeding 99.9 % in full device simulation
ArchitectureElectron shuttling - 2024
Spin-EPR-pair separation by conveyor-mode single electron shuttling in Si/SiGe
Tom Struck, Mats Volmer, Lino Visser, Tobias Offermann, Ran Xue … +5 authors
Shuttle velocity increased by a factor of 10 000 — entanglement still detectable after 3.36 µm
Electron shuttlingMaterials & valley physics - 2022
Conveyor-mode single-electron shuttling in Si/SiGe for a scalable quantum computing architecture
Inga Seidler, Tom Struck, Ran Xue, Niels Focke, Stefan Trellenkamp … +2 authors
99.42 % single-electron shuttling fidelity over a 420 nm quantum bus — driven by four sinusoidal signals
Electron shuttlingArchitecture - 2020
Closed-loop control of a GaAs-based singlet-triplet spin qubit with 99.5% gate fidelity and low leakage
Pascal Cerfontaine, Tim Botzem, Julian Ritzmann, Simon Sebastian Humpohl, Arne Ludwig … +4 authors
99.5 % single-qubit gate fidelity with low leakage, calibrated in a closed loop
Control & readout - 2020
Control Electronics for Semiconductor Spin Qubits
Lotte Geck, Andre Kruth, Hendrik Bluhm, Stefan van Waasen, Stefan Heinen
Requirements and concepts for cryogenic control circuits co-located with the qubit chip
Cryogenic electronicsControl & readout - 2017
Interfacing spin qubits in quantum dots and donors — hot, dense and coherent
Lieven M. K. Vandersypen, Hendrik Bluhm, James S. Clarke, Andrew S. Dzurak, Ryoichi Ishihara … +4 authors
The reference roadmap for integrating spin qubits with classical control hardware
ArchitectureCryogenic electronics
Insights
Thought leadership
Longer-form pieces on where the platform is heading — written for people who read the papers and for those who do not.
MaterialsDraft
The valley problem, mapped
Valley splitting sets the speed limit for coherent transport. Two-dimensional mapping at nanometre resolution turns a material lottery into an engineering parameter.
Error correctionDraft
What fault tolerance actually costs
Surface-code simulations put a number on the shuttling error budget — and the number is more forgiving than the field assumed.